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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Verilog: Port list is on per-line, not same line #12

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

The port list for the module, if long enough, will not be on the same line. This means it'll be on multiple lines.

Determine a way to grab this (or ignore it).

stiggy87 commented 11 years ago

This is fixed, not sure of what commit.