input/output/inout (Verilog) in signal names causes issues

stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.

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input/output/inout (Verilog) in signal names causes issues #13

Open stiggy87 opened 11 years ago

stiggy87 commented 11 years ago

If a user has input/output/inout in names of signals, the current regexp causes it to be grabbed and parsed improperly.

stiggy87 commented 11 years ago

To Do:

Add Regex exception to determine this and then ignore. This may need variable transfers between regex lines.