Verilog macro expansion

stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.

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Verilog macro expansion #14

Open stiggy87 opened 11 years ago

stiggy87 commented 11 years ago

If a user has a macro designated for numbering, it does not translate over to the .veo correctly.

There needs to be a check for Verilog/VHDL macro expansion.

Suggestion: Copy the macro definition into the template and use proper replacement.

stiggy87 commented 11 years ago

To Do:

Copy `define statements into the template
Update parsing algorithm to transfer bus count properly