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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Missing capabilities with styles of Verilog/VHDL #3

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

So far the script only supports this style of Verilog:

module module_name(port_1, port_2, etc..); ... endmodule

This also needs to support any and all variations of VHDL.

stiggy87 commented 11 years ago

Added Verilog parameter capabilities.

aaee12e22de41b27e3d1694b719ac8a945109814

stiggy87 commented 11 years ago

This hopefully closes this issue.

If this is not done, need test case.