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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Repo needs test files #4

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

The repo is missing test Verilog/VHDL files for testing.

stiggy87 commented 11 years ago

Added 4 Verilog tests and 1 VHDL test.

Will revisit when other bugs arise.

stiggy87 commented 11 years ago

This was fixed in 3 commits: 0bf088946cc6d76da25a2b27d515837753c74de6 694038c810abb7f5d9f6e3a6ebbddc7c06d85555 ae63b7715a15027afbd9a4a49973f94ba5f36933