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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Support if there are multiple entities/modules in a file #7

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

A Verilog/VHDL file can contain multiple module/entity definitions. If a user runs in this script, it grabs the first ones only.

Need to identify if there are multiple and either put them in the same .veo/.vho file or separate them out.

stiggy87 commented 11 years ago

This will most likely not make the milestone...

stiggy87 commented 11 years ago

This will not make the mile stone. Pushing out.

stiggy87 commented 11 years ago

As the code stands, the last module in the file is what is captured and outputted.

Idea: Have a count variable to do the work.

To Do:

stiggy87 commented 11 years ago

Does not look like VHDL supports multiple entities in one file unless it is part of a library... To further investigate.

stiggy87 commented 11 years ago

Confirmed that multiple entities in a file are not allowed. Closing issue.