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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Deletion of file (Windows-only) #8

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

This is an odd behavior.

TCL is not closing the file completely. Close the TCLSH fixes issue.

Investigate.

stiggy87 commented 11 years ago

Tested this in PlanAhead/Vivado on Windows, no issue.

TCLSH only issue?

stiggy87 commented 11 years ago

This looks to be an obsolete issue that was fixed when other bugs got fixed.