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stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
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Remove -filetype switch #9

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

Remove the -filetype switch because it is only used in determining which parsing section to use. This can be done by parsing the file name and determining suffix.

Also, to turn this into a Custom Command in PlanAhead/Vivado, this must be removed.

stiggy87 commented 11 years ago

The initial commit of this removal is done. It may not be able to handle every type of Verilog/VHDL extension type. This is to be investigated.

Will close this since it is working, but it can be re-opened if causes more issues.

Commit is here: fc1a9b8b6ccec4e31d0d7ef68a13fea7f87ec07d