We introduce two extension traits that, for STM32F4 parts, introduce a delay before writing to a register. This is to prevent the same register from being written to twice within 4 cycles of REF_CLK. It assumes worst-case setups (180 MHz clock, and 25 MHz REF_CLK), which comes out to a minimum of 29 cycles of delay.
On F1 and F7 parts, the extension traits simply forward the writes
We introduce two extension traits that, for STM32F4 parts, introduce a delay before writing to a register. This is to prevent the same register from being written to twice within 4 cycles of REF_CLK. It assumes worst-case setups (180 MHz clock, and 25 MHz REF_CLK), which comes out to a minimum of 29 cycles of delay.
On F1 and F7 parts, the extension traits simply forward the writes
TODO: