WIP: I2c timing calculation, simple custom algorithm skeleton

[hardfau1t]

a simple way to calculate TIMINGR values.	measured frequancy	expected	%error	after implementation of delay
98.7khz	100khz	1.3%	100.8KHz
282.3khz	300khz	5.9%	301KHz
452.3khz	500khz	9.5%	496KHz
600khz	700khz	14.3%	694KHz
827khz	1Mhz	17.3%	990KHz

i used cheap logic analyzer. result may vary slightly on CRO. higher % of error on high clocks due to tsync time which i ignored it for simplicity. i will add it soon (WIP) also optional duty cycle option is WIP requesting for reviews

solves: #71

[hardfau1t]

also i am little confused why it needs modes, because clearly f7 doesn't has any modes, can run it on any clock speed.

[hardfau1t]

now getting expected clock after introduction of delay. in delay some values are hard-coded like fall time and rise time, analog filter delay is kind of hard-coded. ie T_af is dependent on device, but generally used 70ns if it is active.

[hardfau1t]

EDIT: having some problems at lower frequency of system clock. soon will complete