Invalid clock configuration for apb_clk, apb_tim_clk and core_clk

[keadwen]

G'day

I've identified an inconsistency in the RCC configuration. According to page 166/1390 RM0444 Rev 5, the apb_clk is not driven by sys_freq, but ahb_freq.

In the further review of the RCC configuration freeze, I've noticed 3 separate inconsistencies with the RM0444 and STM32CubeMX Clock Configuration section:

1. apb_clk input is sys_freq (code reference), when it should be ahb_clk.
2. apb_tim_clk is always set as /2 (code reference), when it should be:
   • x1 when apb_psc is x1
   • x2 when apb_psc is x2 or greater
3. core_clk is ahb_freq / 8 (code reference), when it should be either /1 or /8 (while /8 is default).

Image reference from STM32CubeMX for STM32G071GBU6

Thanks, Jakub

[keadwen]

Tiny correction to point 2.

The logic in the code was correct. Only the reference clock was invalid. If a prescaler is set NotDivided then we have /1 (captured in _ match). Otherwise, we do have /2 (captured in other matches).

[keadwen]

@andresv PTAL

[andresv]

@keadwen thanks for finding this out. I'll double check it later.