PLL R/Q outputs have incorrect frequency if requested frequency is less than VCO frequency / 128

[richardeoin]

let ccdr = rcc
        .sys_ck(200.MHz())
        .pll2_p_ck(20.MHz())
        .pll2_r_ck(1.MHz())

The PLL2 VCO frequency is set to 420MHz and therefore the calculated R divider is 0x1A4. The R divider field is only 7 bits wide, so the actual divider programmed is 0x24 and the resulting R ck frequency is 11.7MHz

Instead this configuration should generate an error since it cannot be achieved (minimum VCO frequency is 150MHz and maximum divider 128)