This PR fixes/implements the following bugs/features
[x] Optimize PLL ratio
By setting SRC / M = 2N = 250 for PLL1/2/3 you can flexibly determine clock source frequency and easily calculate division P/Q/R.
CubeMX Screenshots
- for H503KB/H503RB
![image](https://github.com/user-attachments/assets/8e44616c-eb6d-4a9e-aab4-26c23b7dc6c3)
- for H573RI
![image](https://github.com/user-attachments/assets/732b20cc-ecf8-4099-8254-152f99cf04ed)
Basically same as "Optimize PLL ratio" in #2506.
Summary
This PR fixes/implements the following bugs/features
By setting
SRC / M = 2
N = 250
for PLL1/2/3 you can flexibly determine clock source frequency and easily calculate division P/Q/R.CubeMX Screenshots
- for H503KB/H503RB ![image](https://github.com/user-attachments/assets/8e44616c-eb6d-4a9e-aab4-26c23b7dc6c3) - for H573RI ![image](https://github.com/user-attachments/assets/732b20cc-ecf8-4099-8254-152f99cf04ed)