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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `c7590c9` to `310af47` #146

Closed dependabot[bot] closed 1 year ago

dependabot[bot] commented 1 year ago

Bumps neorv32 from c7590c9 to 310af47.

Commits
  • 310af47 Update CONTRIBUTING.md
  • 562d838 implement vectored mtvec (#691)
  • 004e602 [CHANGELOG] add v1.8.9.4
  • d3ec072 [doc] document vectored mtvec mode
  • dd5ec55 [processor_check] add test for vectored mtvec
  • 5ba50a7 [rtl] implement vectored mtvec
  • dc15beb [sw/wdt] minor edits
  • 6d9e034 [docs] RTE uses mtvec in DIRECT mode
  • 062a4f1 [docs] clearify: mtvec only supports DIRECT mode
  • f1e11dd rework watchdog timer and reset system (#692)
  • Additional commits viewable in compare view


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