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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `cff3c3c` to `255eb86` #163

Closed dependabot[bot] closed 11 months ago

dependabot[bot] commented 11 months ago

Bumps neorv32 from cff3c3c to 255eb86.

Commits
  • 255eb86 ⚠️ remove Zifencei generic - Zifencei ISA extension is now always enabled (#709)
  • 800fa68 [changelog] add v1.9.0.3
  • 63219c9 [sw] update processor check program
  • 95b3f9c [docs] Zifencei extension is now always enabled
  • 5109c5e [sim] remove Zifencei generic
  • 31a541e [rtl] remove Zifencei generic
  • b3b2124 :warning: [cpu] remove Zifencei generic
  • See full diff in compare view


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