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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `c85bec3` to `617c8bb` #180

Closed dependabot[bot] closed 10 months ago

dependabot[bot] commented 10 months ago

Bumps neorv32 from c85bec3 to 617c8bb.

Commits
  • 617c8bb [rtl] cleanup & rework/optimize CPU branch system (#735)
  • 987fbb7 [rtl] rework CPU branch system
  • e904b27 [changelog] add v1.9.1.5
  • f7989c9 [rtl] signal renaming
  • 8dfd2d9 🐛 fix bug in instruction-misaligned exception handling (#734)
  • aeb7ba3 [mepc,dpc] mask bit 1 on explicit CSR write if ALIGN = 32
  • 07c8090 [sim] commet fix
  • 776829b mepc & dpc: hardwire bit 1 to zero if IALIGN = 32
  • d48cd5e [revert] re-enable C in Vunit testbench
  • 4f5e83a :bug: [rtl] fix handling of misaligned instruction exception
  • Additional commits viewable in compare view


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