stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `21fea6d` to `682fe6b` #182

Closed dependabot[bot] closed 10 months ago

dependabot[bot] commented 10 months ago

Bumps neorv32 from 21fea6d to 682fe6b.

Commits
  • 682fe6b Update hardware tigger module (Sdtrig) to version 1.0 (#739)
  • 75db870 [docs,ug] add bootloader ERR_EXE note
  • f82b211 [docs] CFS: typo fix
  • f885c58 [rtl] upgrade Sdtrig to v1.0
  • 741805e [sim,sw] add trigger module test case
  • 2578fd9 [docs] update section "trigger module"
  • 737b99c [docs/references] upgrade debug spec.
  • 04d1e10 [changelog] add v1.9.1.8
  • 59c3c2c [sw/examples] remove machine-mode trigger module demo
  • 472fd55 [docs,sw] remove obsolete trigger module CSRs
  • See full diff in compare view


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