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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `446a1b3` to `c303756` #186

Closed dependabot[bot] closed 10 months ago

dependabot[bot] commented 10 months ago

Bumps neorv32 from 446a1b3 to c303756.

Commits
  • c303756 ✨ Add RISC-V Zicond ISA extension (#743)
  • e2416ac [figures] processor: add Zicond ISA block
  • 9e50291 [README] add Zicond
  • f09052e [docs] update ISA sections, add Zicond
  • e02eca5 [changelog] add v1.9.2.1
  • bc7831e [sim] enable Zicond in testbenches
  • b093794 [cpu] add Zicond instructions to back-end
  • d76aa2f [top] add new top generic to enable Zicond
  • a7c093b [rtl] add cp5 (cond)
  • 52c6f22 [rtl] add Zicond co-processor VHDL source
  • Additional commits viewable in compare view


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