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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `3b02874` to `89d0f9d` #275

Closed dependabot[bot] closed 4 months ago

dependabot[bot] commented 4 months ago

Bumps neorv32 from 3b02874 to 89d0f9d.

Commits
  • 89d0f9d [docs/figures] bus: beautification
  • ad8be59 [dcos/reference] cleanup RISC-V specs
  • 28ccc25 [rtl] minor comment cleanup
  • b3f039b [readme] minor cleanup
  • c5f92e0 [Vivado IP] change logo
  • 12a5868 [figures] add smal NEORV32 RISC-V logo
  • 2d29f7c [docs] minor edits
  • 9c403c1 [figures] update Vivado example SoC
  • 92f2e04 [xbus] access type identifier (tag signal) (#917)
  • 2243e39 [Vivado IP] add support for AxPROT signals
  • Additional commits viewable in compare view


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