stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `bc1cf1b` to `bd3afd6` #33

Closed dependabot[bot] closed 1 year ago

dependabot[bot] commented 1 year ago

Bumps neorv32 from bc1cf1b to bd3afd6.

Commits
  • bd3afd6 ✨ Add CFU R4-type instructions (#449)
  • d315351 [docs] update CFU section
  • 23ed2d9 [rtl/core] fix illegal instruction detection
  • 791cfe3 [sw/example] add r4-type instructions to CFU example program
  • b2cece7 [rtl/core] CFU: add r4-type instruction support
  • 2f96296 [rtl/core] FPU: add third register operand
  • 2216799 [rtl/core] add custom-1 opcode (CFU)
  • f1650b8 [rtl] add third register operand infrastructure
  • 9a06cf3 [docs] update Zxcfu section
  • f94a4b6 [CHANGELOG] add v1.7.8.2
  • Additional commits viewable in compare view


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