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stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

Add pointers to this repo in riscof-plugins repo. #5

Closed pawks closed 2 years ago

pawks commented 2 years ago

Would you be willing to add a link pointing to this repo in the readme for riscof-plugins and raise a PR there?

stnolting commented 2 years ago

Sure! I do not have a gitlab account yet, but that shouldn't be a problem.

[...] add a link pointing to this repo in the readme [...]

What format? Just a link with a brief description?

pawks commented 2 years ago

What format? Just a link with a brief description?

Just a table/list pointing to your core and the riscof-plugin for the core.

Also, what was the mechanism you used to dump the signature at the end of simulation?

stnolting commented 2 years ago

Just a table/list pointing to your core and the riscof-plugin for the core.

:+1:

Also, what was the mechanism you used to dump the signature at the end of simulation?

Long story short: the processor (DUT) includes a UART that can be set to "simulation mode". When enabled, all data "send" via the UART is written to a file using VHDL's textio library. Obviously, this only works in simulation.

If you are interested, here are some resources:

stnolting commented 2 years ago

@pawks I am quite new to GitLab, but I think I have successfully opened a PR in https://gitlab.com/incoresemi/riscof-plugins/-/merge_requests/28 😅

pawks commented 2 years ago

Thank you for the PR. It has been merged.