stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
25 stars 6 forks source link

[Dependabot]: Bump neorv32 from `882ddbb` to `d0cd94a` #95

Closed dependabot[bot] closed 1 year ago

dependabot[bot] commented 1 year ago

Bumps neorv32 from 882ddbb to d0cd94a.

Commits
  • d0cd94a ✨ add optional direct memory access controller (DMA) (#593)
  • 8a5c03c [ISA] Zicond extension is frozen now
  • ac0c8f1 [docs] update RISC-V reference specs.
  • 86c0d74 comment fixes
  • 1546c65 [DMA example] add Endianness conversion demo
  • 5276e2a [DMA example program] minor edits
  • 549a4fc [processor_check] minor edits
  • 510c15d [sw] add DMA demo/example program
  • 4d4d1f7 [docs] add DMA
  • 48afcf3 Update README.md
  • Additional commits viewable in compare view


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