stnolting / neorv32-setups

šŸ“ NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
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Can't simulate de0-nano-test-setup with Questa Intel FPGA Edition #191

Open ivanholmes opened 1 week ago

ivanholmes commented 1 week ago

Hi,

I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition but the compilation fails, saying it can't find neorv32_application_image.vhd. The file is definitely in the right place and has the contents one would expect. Quartus 23.1 standard is happy to synthesise the project.

I'm not familiar enough with Questa to know why this is happening - it's probably an error on my part. I'm using Linux as you can tell from the paths in the log reproduced below.

I would appreciate any help or advice! Please let me know if you need any additional information - I will be glad to provide it.

Thanks, Ivan

# //  Questa Intel FPGA Edition-64
# //  Version 2023.3 linux_x86_64 Jul 17 2023
# //
# //  Copyright 1991-2023 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do de0-nano-test-setup_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#   vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Questa Intel FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap work rtl_work 
# Copying /home/ivan/intelFPGA/23.1std/questa_fe/linux_x86_64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlib neorv32
# ** Warning: (vlib-34) Library already exists at "neorv32".
# Errors: 0, Warnings: 1
# vmap neorv32 neorv32
# Questa Intel FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap neorv32 neorv32 
# Modifying modelsim.ini
# vcom -2008 -work neorv32 {/home/ivan/Documents/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd}
# Questa Intel FPGA Edition-64 vcom 2023.3 Compiler 2023.07 Jul 17 2023
# Start time: 15:55:45 on Sep 19,2024
# vcom -reportprogress 300 -2008 -work neorv32 /home/ivan/Documents/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd 
# -- Loading package STANDARD
# -- Compiling package body neorv32_application_image
# ** Error: (vcom-11) Could not find work.neorv32_application_image.
# ** Note: /home/ivan/Documents/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd(8): VHDL Compiler exiting
# End time: 15:55:45 on Sep 19,2024, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: /home/ivan/intelFPGA/23.1std/questa_fe/linux_x86_64/vcom failed.
# Error in macro ./de0-nano-test-setup_run_msim_rtl_vhdl.do line 10
# /home/ivan/intelFPGA/23.1std/questa_fe/linux_x86_64/vcom failed.
#     while executing
# "vcom -2008 -work neorv32 {/home/ivan/Documents/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd}"
stnolting commented 1 week ago

Hey @ivanholmes.

I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition

Did you use the TCL script to setup the project?

[...] it can't find neorv32_application_image.vhd.

Looking at the log, this seems a bit strange to me:

** Error: (vcom-11) Could not find work.neorv32_application_image.

Seems like Questa is expecting this specific file to be part of the standard work library, however it should be in neorv32. So maybe it is just a setup issue?!

All rtl files need to be added to a new VHDL library named neorv32: https://github.com/stnolting/neorv32-setups/blob/9a23f3e47579c2ce15a0ed6370467f738423e69e/quartus/de0-nano-test-setup/create_project.tcl#L63

ivanholmes commented 1 week ago

Hi @stnolting, thanks for your quick and helpful response!

I did use the TCL script, and the line: set_global_assignment -name VHDL_FILE ./../../neorv32/rtl/core/neorv32_application_image.vhd -library neorv32 is present in the de0-nano-test-setup.qsf file.

It's useful that you noticed Questa is expecting neorv32_application_image to be part of the work library. This gives me something to investigate! It seems I misread the error message, interpreting it as Questa being unable to find the .vhd file, which isn't the issue here. In fact, I have a feeling that it's nothing to do with the specific file but just a misconfiguration of Questa.

I'll look into it early next week and see how I get on.

stnolting commented 19 hours ago

I'll look into it early next week and see how I get on.

Great! Keep us updated! This project is intended to work "out-of-the-box" - so we'll make every effort to ensure that this really works. :wink: And feel free to ask if you have further questions.