Closed ivanholmes closed 1 week ago
Hey @ivanholmes.
I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition
Did you use the TCL script to setup the project?
[...] it can't find neorv32_application_image.vhd.
Looking at the log, this seems a bit strange to me:
** Error: (vcom-11) Could not find work.neorv32_application_image.
Seems like Questa is expecting this specific file to be part of the standard work
library, however it should be in neorv32
. So maybe it is just a setup issue?!
All rtl files need to be added to a new VHDL library named neorv32
:
https://github.com/stnolting/neorv32-setups/blob/9a23f3e47579c2ce15a0ed6370467f738423e69e/quartus/de0-nano-test-setup/create_project.tcl#L63
Hi @stnolting, thanks for your quick and helpful response!
I did use the TCL script, and the line:
set_global_assignment -name VHDL_FILE ./../../neorv32/rtl/core/neorv32_application_image.vhd -library neorv32
is present in the de0-nano-test-setup.qsf file.
It's useful that you noticed Questa is expecting neorv32_application_image to be part of the work
library. This gives me something to investigate! It seems I misread the error message, interpreting it as Questa being unable to find the .vhd
file, which isn't the issue here. In fact, I have a feeling that it's nothing to do with the specific file but just a misconfiguration of Questa.
I'll look into it early next week and see how I get on.
I'll look into it early next week and see how I get on.
Great! Keep us updated! This project is intended to work "out-of-the-box" - so we'll make every effort to ensure that this really works. :wink: And feel free to ask if you have further questions.
First of all, sorry for the massively late reply - real life got in the way as always! I've been playing around with Questa and I haven't been able to figure out how to tell it that this file (and presumably all the others from the neorv32 library) should be compiled as such, and not as part of the work library.
I'm at a bit of a loss now. Do you have any ideas? Is there any info I could provide you with that might help?
In the meantime, I have sent a PR #197 to correct some minor issues I had to fix before getting to this point! :)
I've found a workaround. After deleting my clone of the repo and starting again, I got a little bit further with Questa. It turns out that the order of files in the de0-nano-test-setup_run_msim_rtl_vhdl.do
file (that Quartus NativeLink generates for Questa) is very important.
The version that my project generates now looks like this:
transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlib neorv32
vmap neorv32 neorv32
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_bootloader_image.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_sys.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_crypto.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_xbus.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_onewire.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_pmp.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_xirq.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_debug_auth.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_clockgate.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cfs.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_imem.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_cond.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_pwm.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_decompressor.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_boot_rom.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_wdt.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_dma.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_debug_dtm.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_lsu.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_gpio.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_bus.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_mtime.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_gptmr.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_sysinfo.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_dmem.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_fifo.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_regfile.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_crc.vhd}
vcom -93 -work work {/home/ivan/University/PhD/Technical_tests/neorv32-setups/quartus/de0-nano-test-setup/neorv32_test_setup_bootloader.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_alu.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_sdi.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_uart.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cache.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_slink.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_neoled.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu_control.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_twi.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_spi.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_debug_dm.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_cpu.vhd}
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_top.vhd}
This compiles neorv32_cpu_cp_cfu.vhd
just fine but fails on neorv32_application_image.vhd
as before. However, if I manually force it to compile neorv32_package.vhd
first, by running
vcom -93 -work neorv32 {/home/ivan/University/PhD/Technical_tests/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd}
then rerun the de0-nano-test-setup_run_msim_rtl_vhdl.do
file, everything works. Subsequent attempts to launch NativeLink also work fine because the database knows about neorv32_package
now.
I still have no idea how to get Quartus to generate this file in the correct order (it doesn't seem tied to de0-nano-test-setup.qsf
in any way), but at least there's a workaround! Thanks for your assistance.
It turns out that the order of files in the de0-nano-test-setup_run_msim_rtl_vhdl.do file (that Quartus NativeLink generates for Questa) is very important.
Some tools can figure out the compile order by themself, other tools require an explicit definition of it. That is why we have added *.f
files like rtl/file_list_soc.f
. As an example, the TCL script that is used for building the Vivado IP module reads this list:
# read and process NEORV32 SoC file list
set file_list_file [read [open "$neorv32_home/rtl/file_list_soc.f" r]]
set file_list [string map [list "NEORV32_RTL_PATH_PLACEHOLDER" "$neorv32_home/rtl"] $file_list_file]
puts "NEORV32 source files:"
puts $file_list
add_files $file_list
set_property library neorv32 [get_files $file_list]
Maybe you can use that concept for your Quartus setup? I mean, the TCL should be compatible, right?
Sorry for the late reply (again). I agree that your idea of using a file list should work. Unfortunately I haven't been able to get it to work with Quartus NativeLink.
It says it supports running a testbench script (where I could include some TCL code that loads the file list) but it seems to just ignore it and use the broken one (that it generates according to an unknown order like before). I might look into it more later, but I think I've exhausted my options so will just use my workaround from before.
Thanks for your assistance and giving your time to help me. I really appreciate it!
I have never used Quartus NativeLink, so I am not familiar with the simulation flow. I am using AMD ISIM, GHDL and Cadence simulation solutions - all using the file lists included in this project. And so far everything seems to work fine... 🤔
And sorry for the late reply 🙈
No problem! I do find that the issue with things like NativeLink is that they make things easier... until it starts to get really complex and they just obscure what's going on. I'll report back if I have any success with it later in my project.
Hi,
I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition but the compilation fails, saying it can't find neorv32_application_image.vhd. The file is definitely in the right place and has the contents one would expect. Quartus 23.1 standard is happy to synthesise the project.
I'm not familiar enough with Questa to know why this is happening - it's probably an error on my part. I'm using Linux as you can tell from the paths in the log reproduced below.
I would appreciate any help or advice! Please let me know if you need any additional information - I will be glad to provide it.
Thanks, Ivan