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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `e854085` to `bb4d780` #101

Closed dependabot[bot] closed 4 months ago

dependabot[bot] commented 4 months ago

Bumps neorv32 from e854085 to bb4d780.

Commits
  • bb4d780 [readme] minor edits
  • 0fd4d72 [readme] minor cleanups
  • 5194bf5 Minor rtl edits/cleanups (#931)
  • fdf220c [changelog] add v1.10.0.4
  • 8ab8b97 [rtl] FIFO remove redundant output register
  • c0b8020 [rtl] cleanup README
  • 46aff57 [rtl] code cleanups
  • f4bcc2f Add UART FIFO clear flags; add DMA FIRQ interrupt configuration (#930)
  • 3d7ffa1 [sw/example] update processor_check program
  • 90bd073 [sw] extend DMA example
  • Additional commits viewable in compare view


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