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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `d8f46ac` to `9700121` #114

Closed dependabot[bot] closed 1 month ago

dependabot[bot] commented 1 month ago

Bumps neorv32 from d8f46ac to 9700121.

Commits
  • 9700121 :bug: fix B.CTZ decoding regression bug (#1018)
  • 8e748e5 [changelog] add v1.10.3.8
  • 4de6a5f :bug: [control] fix CTZ decoding
  • a1f3c5f ⚠️ Refactor RTL files / hierarchy (#1017)
  • d8dfee7 [docs] soc: update reset/clock sections
  • 89e880e [docs] update file list
  • bcb609d [changelog] add v1.10.3.7
  • d4e4f62 [rtl] update SoC HDL file list
  • f09adfc [package] update version ID
  • fa30354 [rtl] add new file: system infrastructure modules
  • Additional commits viewable in compare view


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