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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
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Convert cores and memory vhd separately ? #46

Closed fortyone041 closed 8 months ago

fortyone041 commented 1 year ago

Hi, just wanted to ask how can I convert the core vhd files and the memory vhd files into verilog separately ?

umarcor commented 1 year ago

See https://github.com/stnolting/neorv32-verilog/blob/main/src/convert.sh#L28 and https://ghdl.github.io/ghdl/using/Synthesis.html#synthesis-synth.

stnolting commented 1 year ago

Hey there!

Of course you can use the same setup as we are doing in this project.

What is your actual use case? As an alternative option you could disable the processor's internal memories and attach your custom Verilog memory modules via the external bus interface.