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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `486087e` to `bfc4b60` #67

Closed dependabot[bot] closed 11 months ago

dependabot[bot] commented 11 months ago

Bumps neorv32 from 486087e to bfc4b60.

Commits
  • bfc4b60 [rtl] minor assertion typo fix
  • 5a827ea [XIP] add clock divider for fine-tuning (#731)
  • d456177 [sw] update SVD dile
  • 4222dd7 [sw] update XIP demo program
  • fed34aa update bootloader (XIP setup function)
  • 44498f5 [changelog] add v1.9.1.2
  • a5ebcc7 [XIP] add clock divider for fine-tuning
  • 56a30c9 [SPI] re-add high-speed mode (#730)
  • 16ed6ca [spi] add output registers for CS lines
  • 8c499c5 [changelog] add v1.9.1.1
  • Additional commits viewable in compare view


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