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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `80cc23c` to `0ab5863` #74

Closed dependabot[bot] closed 9 months ago

dependabot[bot] commented 9 months ago

Bumps neorv32 from 80cc23c to 0ab5863.

Commits
  • 0ab5863 🚀 preparing release v1.9.3
  • 1f4ea48 [rtl] fix minor VHDL coding style issue (#763)
  • 9308724 [CHANGELOG] add v1.9.2.11
  • 20c6633 [rtl] fix minor VHDL coding style issue
  • 9d61af2 [rtl/core] add again mtime_o to top entity (#762)
  • b5e791a [docs] add mtime system time output
  • 1d0f142 [mtime] comment fixes
  • 5736de0 [rtl] rename mtime output
  • 6082304 [sim] add system time output (yet unused)
  • e913d67 [top] rename mtime output
  • Additional commits viewable in compare view


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