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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `bf82ad6` to `f6ea5b9` #80

Closed dependabot[bot] closed 8 months ago

dependabot[bot] commented 8 months ago

Bumps neorv32 from bf82ad6 to f6ea5b9.

Commits
  • f6ea5b9 [docs] minor fixes and edits
  • 0fe0ef9 [rtl] minor comment edits
  • 36dbac6 [rtl/README] minor edits
  • 3ca8578 [.github] update download-artifact action to v4
  • cfc2db0 [.github] update upload-artifact action to v4
  • d375493 :warning: Rework hardware performance monitor (HPM) events (#811)
  • 2839ab4 Merge branch 'main' into rework_hpm
  • 772e0e2 :bug: Fix bug in CRT0 trap handler (#812)
  • b862aea [rtl] update pre-built memory images
  • 8f3a2c3 :bug: fix crt0 trap handler
  • Additional commits viewable in compare view


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