CPU_EXTENSION_RISCV_B NOT enabled in neorv32_verilog_wrapper.vhd

[ucycg]

In the wrapper file for the example processor config the FAST_SHIFT_EN is set true while the CPU_EXTENSION_RISCV_B is not existent in this file. Is this just a "typo" or what is the reasoning behind it? If there is any I would like to understand that.

Is it the idea hey the fast barrel shifter dedicated hardware unit is used also in the execution of other instructions that the ones contained in the RISCV_B extension?

[stnolting]

Hey @ucycg!

In the wrapper file for the example processor config the FAST_SHIFT_EN is set true while the CPU_EXTENSION_RISCV_B is not existent in this file. Is this just a "typo" or what is the reasoning behind it? If there is any I would like to understand that.

The default wrapper just shows an arbitrary configuration example.

Btw, all the generics / configuration options that are not listed explicitly within the wrapper use the default configuration from the processor's top entity: https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_top.vhd#L46

Is it the idea hey the fast barrel shifter dedicated hardware unit is used also in the execution of other instructions that the ones contained in the RISCV_B extension?

Right, the FAST_SHIFT_EN option is used by

• the B (bit-manipulation) shift instructions: https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_cpu_alu.vhd#L242
• the RVI/RVE (base ISA) shift instructions: https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_cpu_alu.vhd#L211

[ucycg]

Okay thank you Stephan for the clarifitcation :)