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stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `0a0afa1` to `b3eb764` #88

Closed dependabot[bot] closed 7 months ago

dependabot[bot] commented 7 months ago

Bumps neorv32 from 0a0afa1 to b3eb764.

Commits
  • b3eb764 :bug: fix DMA fence flag, :warning: rework CPU FIRQs (#864)
  • 58ce2dd [sw] minor edits / cleanups
  • 62bbb36 [docs] SoC FIRQs: minor edits
  • df4dedc [rtl] mip CSR is now read-only
  • ff748ec [changelog] add v1.9.7.5
  • 59b1c59 [sw] update DMA demo
  • a64a660 [rte] update debug handler
  • 52aef16 [sw/lib] remove CPU IRQ en/dis functions
  • 419908c :bug: [rtl] fix DMA fence flag
  • 9a6f962 [sw/example] update SPI trap handler
  • Additional commits viewable in compare view


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