stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `49bc8be` to `a6b0d6e` #94

Closed dependabot[bot] closed 6 months ago

dependabot[bot] commented 6 months ago

Bumps neorv32 from 49bc8be to a6b0d6e.

Commits
  • a6b0d6e Add NEORV32 as Vivado IP (#894)
  • fd88f5d [docs] minor clean-up
  • 236de30 [rtl/system_integration] minor cleanups
  • ed71771 [docs] update user guide: vivado ip packaging
  • 1bce216 [rtl] update version ID
  • bf4b0f1 [changelog] add v1.9.9.1
  • 8d9336a [docs] update Vivado IP figures
  • 847a424 :sparkles: [rtl] add initial IP packaging script
  • dc096c9 [rtl] update Vivado IP top
  • d47e6da [rtl] rework AXI/Vivado-IP wrapper
  • Additional commits viewable in compare view


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