stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
https://github.com/stnolting/neorv32
BSD 3-Clause "New" or "Revised" License
62 stars 13 forks source link

[Dependabot]: Bump neorv32 from `a6b0d6e` to `c6ebc0f` #95

Closed dependabot[bot] closed 5 months ago

dependabot[bot] commented 5 months ago

Bumps neorv32 from a6b0d6e to c6ebc0f.

Commits
  • c6ebc0f [vivado ip] fix configuration gui
  • e4f2e52 [Vivado IP] fix JTAG reset default value
  • 288b55d [rtl/system_integration] add README
  • a1c7709 [readme] add link to Vivado IP packaging
  • See full diff in compare view


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