search

stnolting / neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
https://neorv32.org
BSD 3-Clause "New" or "Revised" License
1.58k stars 223 forks source link

A question on fence and fence.i #1061

Closed mahdi259 closed 2 days ago

mahdi259 commented 3 days ago

Describe the bug Hi. As you described in datasheet, fence and fence.i instructions act in the same manner.

The NEORV32 treats both fence instructions (fence = data fence, fence.i = instruction fence) in exactly the same way. Both instructions cause a flush of the CPU’s instruction prefetch buffer and also send a fence request via the system bus (see Bus Interface). This system bus fence operation will, for example, clear/flush all downstream caches.

My understanding is that it doesn't matter if you execute fence or fence.i instruction. Executing each of them clears all caches (dcache, icache, and xcache) and instruction prefetch buffer. But isn't fence.i specifically for instruction cache? and fence for data cache?

Thanks

stnolting commented 3 days ago

My understanding is that it doesn't matter if you execute fence or fence.i instruction. Executing each of them clears all caches (dcache, icache, and xcache) and instruction prefetch buffer.

That's right - at least for NEORV32.

However, to keep you code platform-independent (and to make clear you intention of each FENCE operation) I recommend to keep using individual fence and fence.i instructions.

But isn't fence.i specifically for instruction cache? and fence for data cache?

It's difficult to generalize, because it depends a lot on the platform.

On a single-hart setup (just one CPU core; no other instances that can alter memory) fence can be implemented as simple nop. On another single-hart platform a fence might put the CPU into halt mode until outstanding DMA transfers have completed...

mahdi259 commented 2 days ago

Sorry I didn't got the point with nop. If fence flushes caches, then how it can be implemented with nop?

stnolting commented 2 days ago

If a platform does not have any caches nor any other mechanism that might cause outstanding or re-ordering of memory accesses any FENCE instruction can also be implemented as nop because there is nothing a fence could do.

stnolting commented 2 days ago

Furthermore, the point that fence instructions cause cache flushes is also platform-specific and not explicitly dictated by the RISC-V spec. To be precisely, there is an additional ISA extension that contain all the cache management operations.

mahdi259 commented 2 days ago

Thanks a lot