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stnolting / neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
https://neorv32.org
BSD 3-Clause "New" or "Revised" License
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Bootloader blockage while executing binary #1078

Open mahdi259 opened 1 week ago

mahdi259 commented 1 week ago

Is your feature request related to a problem? Please describe. Hi I'm trying to use external SRAM memory instead of internal IMEM. The problem is that it's blocked at Booting from 0x00000000 after uploading and clicking e. I found out that SRAM memory is not cleared after power off and addresses beyond program binary contain non zero data. Is it necessary that they get zero?

(I checked memory values by bus_explorer in external flash (XIP method), and the application binary is placed correctly in SRAM.)

mahdi259 commented 1 week ago

I cleared SRAM manually and then uploaded binary file. Although other memory values are zeroed, it is again blocked at Booting from 0x00000000.

mahdi259 commented 1 week ago

After enabling XBUS_CACHE_EN, it works now! Does anyone have any idea about the reason of blockage in case of not using XBUS cache?!

stnolting commented 3 days ago

The problem is that it's blocked at Booting from 0x00000000

This can have a lot of reasons... At first, the (external) DMEM is used to setup the stack. If that already fails the further boot process crashes.

I found out that SRAM memory is not cleared after power off and addresses beyond program binary contain non zero data. Is it necessary that they get zero?

Basically, no memory is cleared nor have to be cleared at all except for the .bss segment. See :books: 4.7. Start-Up Code (crt0)

(I checked memory values by bus_explorer in external flash (XIP method), and the application binary is placed correctly in SRAM.)

Did you also try to access the external SRAM with the bus explorer?

After enabling XBUS_CACHE_EN, it works now! Does anyone have any idea about the reason of blockage in case of not using XBUS cache?!

This might be caused by the SRAM controller. Maybe it does not support single-word accesses (and just block accesses that are used by the cache)?