simulation cycle signal of instruction memory

stnolting / neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

https://neorv32.org

BSD 3-Clause "New" or "Revised" License

1.61k stars 228 forks source link

simulation cycle signal of instruction memory #153

Closed rafaelcorsi closed 3 years ago

rafaelcorsi commented 3 years ago

The external Instruction memory (a) should check for the it valid cycle signal not for the b external memory signal:

https://github.com/stnolting/neorv32/blob/3be750c5e286aca58ae488a78dbecb9ade105269/sim/neorv32_tb.vhd#L544

+(wb_mem_a.cyc = '1')
-(wb_mem_b.cyc = '1')

If its is correct I could generate a PR.

all the best,

stnolting commented 3 years ago

You are right, this seems to be a typo 🙈

If its is correct I could generate a PR.

:+1: