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stnolting / neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
https://neorv32.org
BSD 3-Clause "New" or "Revised" License
1.55k stars 214 forks source link

Neorv32 synthesis in Design compiler #884

Closed mahdi259 closed 4 months ago

mahdi259 commented 4 months ago

Hi, This is actually a question. I have synthesized Neorv32 in Design Compiler. My problem is with the resulting design file that I produce with design compiler. It actually gives 'X' signal in simulation for some outputs. Have you ever synthesized Neorv32 in Design compiler @stnolting? Thanks

stnolting commented 4 months ago

You mean Synopsys Desgin Compiler? Unfortunately, I have never used that...

It actually gives 'X' signal in simulation for some outputs.

Which signals are we talking about? Can you see the core doing anything useful, e.g. booting up?

mahdi259 commented 4 months ago

Yes, I synthesized the same neorv32_top that I used in neorv32_tb_simple. The UART signals are getting 'X'. If I solve it, I will describe the issue here.

mahdi259 commented 4 months ago

The problem was with hold time of implementation. I relaxed the constraints and it worked.

stnolting commented 4 months ago

Great to hear! :+1:

mahdi259 commented 4 months ago

Hi @stnolting Do you have a friend that is familiar with synopsis DC?

stnolting commented 4 months ago

Unfortunately not. 🙈 But maybe someone else here can help?!

mahdi259 commented 4 months ago

Ok thanks

mahdi259 commented 4 months ago

For anyone who reads this later. Generating sdf file of synthesized design and using it for simulation in Questasim improves maximum operational frequency of design.