VUnit simulation failure

[DatNguyen97-VN]

Dear Admin,,,

Describe the bug I running the script ./sim/run.py -v for VUnit test and this message after running the simulation GHDL Bug occurred. :cry:

Expected behavior

Compiling into neorv32: rtl/core/mem/neorv32_imem.legacy.vhd                         passed
Compiling into neorv32: rtl/core/mem/neorv32_imem.default.vhd                        passed
Compiling into neorv32: rtl/core/mem/neorv32_dmem.legacy.vhd                         passed
Compiling into neorv32: rtl/core/mem/neorv32_dmem.default.vhd                        passed
Compiling into neorv32: sim/neorv32_tb.vhd                                           passed
Compile passed

Running test: neorv32.neorv32_tb.all
Running 1 tests

Starting neorv32.neorv32_tb.all
Output file: /mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/test_output/neorv32.neorv32_tb.all_c3cfea2df17f700e2ad73ed9f0ea1f547c1f07ce/output.txt

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 2.0.0-dev (tarball) [Dunoon edition] open-tool-forge.nightly-20211006
Compiled with GNAT Version: 9.3.0
Target: x86_64-linux-gnu
/mnt/d/VLSI/soc/neorv32_sim/neorv32/
Command line:
/home/tools/fpga-toolchain/fpga-toolchain/bin/ghdl --elab-run --std=08 --work=neorv32 --workdir=/mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/ghdl/libraries/neorv32 -P/mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/ghdl/libraries/vunit_lib -P/mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/ghdl/libraries/osvvm -P/mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/ghdl/libraries/neorv32 neorv32_tb neorv32_tb_rtl --max-stack-alloc=256 -gci_mode=False -grunner_cfg=active python runner : true,enabled_test_cases : ,output path : /mnt/d/VLSI/soc/neorv32_sim/neorv32/vunit_out/test_output/neorv32.neorv32_tb.all_c3cfea2df17f700e2ad73ed9f0ea1f547c1f07ce/,tb path : /mnt/d/VLSI/soc/neorv32_sim/neorv32/sim/,use_color : true --assert-level=error --ieee-asserts=disable
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : ortho_code-x86-emits.adb:1724
Call stack traceback locations:
0x865ba2 0x4e805d 0x4ea00c 0x4eb189 0x4ebe29 0x4ebfdb 0x4dd2f6 0x4f56ed 0x7e7975 0x7969f7 0x7dc2ed 0x796a52 0x7e88e3 0x754db3 0x752562 0x7606ec 0x7f42c9 0x730ae9 0x664731 0x7f7c1a 0x405823 0x8936ee 0x403eec
******************************************************************
fail (P=0 S=0 F=1 T=1) neorv32.neorv32_tb.all (1.9 seconds)

==== Summary ==================================
fail neorv32.neorv32_tb.all (1.9 seconds)
===============================================
pass 0 of 1
fail 1 of 1
===============================================
Total time was 1.9 seconds
Elapsed time was 1.9 seconds
===============================================
Some failed!

Please help me again... :smiley:

[Unike267]

Hi @DatNguyen97-VN !

Make sure that the application_image.vhd file is a proper file to perform the simulation. (The simulation is developed for the software processor_check and hello_world), see #816.

I recommend you to follow step by step the workflow for VUnit simulation.

That is, build the program with the right architecture:

 make -C sw/example/processor_check
          clean_all
          USER_FLAGS+=-DUART0_SIM_MODE
          USER_FLAGS+=-DSUPPRESS_OPTIONAL_UART_PRINT
          USER_FLAGS+=-flto
          MARCH=rv32imac_zicsr_zifencei
          info
          all

For this purpose you can use the following container:

• docker://ghcr.io/stnolting/neorv32/sim

Using for example the following code:

podman run --rm -itv $(pwd):/wrk:z -w /wrk stnolting/neorv32/sim  make -C sw/example/{ANY_SW_FOLDER} clean_all USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-DSUPPRESS_OPTIONAL_UART_PRINT USER_FLAGS+=-flto MARCH=rv32imac_zicsr_zifencei info all

(Here I've used podman but it would be the same for docker.)

And run the simulation:

./sim/run.py --ci-mode -v

I just checked in local and the simulation works properly. As shown in the following images:

I hope you find it helpful,

Cheers! 😃