stnolting / riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
GNU General Public License v2.0
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Simulate Bootloader functionality with Testbench #4

Closed ucycg closed 7 months ago

ucycg commented 1 year ago

I'm currently running the NEORV32 Code via Cadence xcelium and was able to simulate successfully the blinky LED example via the application image.

Is there anything on the Github that lets me test the bootloader by sending a code example via uart to the processor and all of this inside Cadence Xcelium? My idea so far would be to write my own UART TX module as part of a testbench somehow that transmits the Code to the CPU with the bootloader code.

If there is anything like this already existing I would be glad to know that or if you think there is a better idea to do what I want to do.

The final goal for me is to do a physical chip design with the NEORV32

stnolting commented 1 year ago

Hey @ucycg!

I'm currently running the NEORV32 Code via Cadence xcelium and was able to simulate successfully the blinky LED example via the application image.

Great to hear!

s there anything on the Github that lets me test the bootloader by sending a code example via uart to the processor and all of this inside Cadence Xcelium? My idea so far would be to write my own UART TX module as part of a testbench somehow that transmits the Code to the CPU with the bootloader code.

No, there is nothing like that yet. However, I was playing with such a setup but I did not make its way to repository. But as you already mentioned, that is just a simple UART TX module that send data read from a file (the image file).

I will put that onto my todo list :wink: