Power improvements on backplane

[dcstraney]

• [ ] Swap input ring terminal polarity to match adjacent power connectors
• [x] Reduce 10Ω series resistor (R5) to 1Ω
• [x] Replace FPGA_Vin regulator with a TO-252 BJT & zener diode on base; as-is, either have to manually bypass it when Vin < 17V, or it drops ~2V @ lower input voltages, wasting significant power. Conducting 300 mA @ ß=20 req. Ib=15 mA → Rbase=20Ω for 0.3V drop (1V total drop); this doesn't work for higher input voltages (24V, for example). May be better low-dropout voltage-limiting schemes.

[dcstraney]

FPGA_Vin OVP: MJB44H11 has min. ß≈60 @ 300 mA (extrapolated from 2A) so 60Ω Rbase (5 mA) for same conditions; much closer. Series base resistor & JFET or depletion-mode MOSFET for current-limiting?

[dcstraney]

Have to take voltage limiter dissipation into account; drawing 300 mA through a 24V-to-15V drop will dissipate 2.7W.

• Copper planes max. out @ ~40 K/W, which is still too much (+108 K Tj rise)
• Need a TO-220 + "medium-size" heatsink (such as CTS 7-340-1PP-BA) with 15 K/W, as this only has +40 K Tj rise
• Or a D2Pak + SMT heatsink such as Wakefield-Vette 218-40CTE5; claims 17 K/W