Open dcstraney opened 1 month ago
FPGA's internal clock management blocks can't deal with a 10 Mhz input very well (adds significant jitter, etc.): add an external clock multiplier IC to boost the clock frequency by 2.5x min. (5x?) before sending to the FPGA.
FPGA's internal clock management blocks can't deal with a 10 Mhz input very well (adds significant jitter, etc.): add an external clock multiplier IC to boost the clock frequency by 2.5x min. (5x?) before sending to the FPGA.