Vivado 19.2 Upgrade IP issues

[tanman777]

Do you folks know what the comparable upgrade to would be from 18.3 to 19.2: 'axi_qpsk_rx_csync_bd_axi_qpsk_rx_csync_1_0' 'axi_qpsk_rx_dec_bd_axi_qpsk_rx_dec_1_0' axi_qpsk_rx_rrc_bd_axi_qpsk_rx_rrc_1_0' 'axi_qpsk_rx_tsync_bd_axi_qpsk_rx_tsync_1_0' 'qpsk_tx_symbol_gen_bd_qpsk_tx_symbol_gen_1_0' 'axi_qpsk_rx_csync_0' 'axi_qpsk_rx_dec_0' 'axi_qpsk_rx_rrc_0' 'axi_qpsk_rx_tsync_0' 'qpsk_tx_symbol_gen_0'

Or definitions of the clock, sync settings would help to move this to 19.2.

[jogomojo]

Hi there tanman,

All the System Generator IPs should be valid for Vivado 19.2. I have not been able to look at this myself and, until the global health crisis has subsided, I won't be able to check for you. Have you tried this yourself? I'm not sure what you mean by clock and sync settings?

There was an issue when we upgraded the project from 18.1 to 18.2 as the minimum sample frequency of the DAC was increased from 500Msps to 1000Msps, but this only affected the Vivado block design, not any of the sysgen IPs. I'm not aware of any substantial changes to the Xilinx IPs in Vivado 19.2 that couldn't be fixed by using the 'Upgrade IP' dialogue.

josh

[tanman777]

Many thanks for the reply.

I cannot upgrade the IP's for the files I posted. All the rest are sub-structured under. I can post the IP error if you wish from 19.2

I also cannot see the DAC module at present without updating all of the "qpsk" files I posted.

One idea would be for me would be to revert back to 18.3 version of Vivado, which I can do on Linux and see it it works.

Thanks.

Tanay (aka tanman)

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Tanay Bhatt, Ph.D., P.E. 214-986-2498

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From: Josh Goldsmith notifications@github.com Sent: Wednesday, March 25, 2020 8:33 AM To: strath-sdr/rfsoc_qpsk rfsoc_qpsk@noreply.github.com Cc: tanman777 tbhatt@astrapi-corp.com; Author author@noreply.github.com Subject: Re: [strath-sdr/rfsoc_qpsk] Vivado 19.2 Upgrade IP issues (#28)

Hi there tanman,

All the System Generator IPs should be valid for Vivado 19.2. I have not been able to look at this myself and, until the global health crisis has subsided, I won't be able to check for you. Have you tried this yourself? I'm not sure what you mean by clock and sync settings?

There was an issue when we upgraded the project from 18.1 to 18.2 as the minimum sample frequency of the DAC was increased from 500Msps to 1000Msps, but this only affected the Vivado block design, not any of the sysgen IPs. I'm not aware of any substantial changes to the Xilinx IPs in Vivado 19.2 that couldn't be fixed by using the 'Upgrade IP' dialogue.

josh

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[dnorthcote]

Closed as this project does not support Vivado 19.2.