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strath-sdr / rfsoc_sam

RFSoC Spectrum Analyser Module on PYNQ.
BSD 3-Clause "New" or "Revised" License
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Vivado block design file (rfsoc_sam.xpr) #20

Closed alireza1325 closed 1 year ago

alireza1325 commented 1 year ago

Hello,

Thank you so much for providing the VHDL code of this project. I watched the youtube video (https://www.youtube.com/watch?v=PqPdfnbNxyY) where you described the block design of the project (rfsoc_sam.xpr). However, I couldn't fine the corresponding file in this github repo. Could you please upload it as well?

Thanks, Ali

dnorthcote commented 1 year ago

Hi Ali,

Nice to hear from you and I'm glad the resources have been useful so far.

We don't provide the .xpr project in the repository. Instead, we provide the source files that let you generate an .xpr project.

The .xpr project can be generated by following the instructions in the ReadMe.md.

The block design is contained in the relevant .tcl file for your development board. For instance, the RFSoC4x2 .tcl file is here https://github.com/strath-sdr/rfsoc_sam/blob/master/boards/RFSoC4x2/rfsoc_sam/rfsoc_sam.tcl

Let me know if this resolves your issue,

Thanks, David.

dnorthcote commented 1 year ago

Closing this issue as resolved.