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stremovsky / moneroasic

Cryptonight Monero Verilog code for ASIC
GNU General Public License v3.0
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ASIC Physical Design #4

Open abdelazeem201 opened 1 year ago

abdelazeem201 commented 1 year ago

Hey Yuli,

I am gonna use this project through ASIC Design Approach, Do you have any Tips for me?

Like Did you decide the Clock frequency?, Did you have any cloudy logic that take more than one Clock cycle?

stremovsky commented 1 year ago

Hello

I am not sure the code is relevant, may be part of it.

I never reached the hardware step - so I do not know about timing for a real ASIC.

A new idea I was thinking about - use memory based CPU instead of ASIC (they are called APU). This way you get extra accelerated speed when working with memory and you can change the code if needed.

For example, GSI Technology makes such chips.

They are used by AI experts.

So, if you have budget to do the POC, lets have a chat about it.

Best regards,

Yuli

@.***

On Mon, Apr 10, 2023, 23:41 Ahmed Abdelazeem @.***> wrote:

Hey Yuli,

I am gonna use this project through ASIC Design Approach, Do you have any Tips for me?

Like Did you decide the Clock frequency?, Did you have any cloudy logic that take more than one Clock cycle?

— Reply to this email directly, view it on GitHub https://github.com/stremovsky/moneroasic/issues/4, or unsubscribe https://github.com/notifications/unsubscribe-auth/ADEFWYVBZLJKSIULYTKO5J3XARV6RANCNFSM6AAAAAAWZMVRIU . You are receiving this because you are subscribed to this thread.Message ID: @.***>