Closed bkukanov closed 6 years ago
we need to add MAC Address, SATA interface & clock synthesizer schematic design
JTAG header not connected
The MIO parts have to be connected fully and re-analyzed. Zynq PL side has to be connected
While compiling project there are some duplicate net errors
There are PL DDR4 duplicate net errors
@metinburak PMOD_ARD_RASP hasn't connected to the Zynq IO
Mechanical mounting holes are required to added
done
The Subutai Router v2.0 schematic design will be analysed for compatibly of peripherals and checked the design