[#14] Test RP2A03 divider

[sieken]

Parent issue: #14

Test that the RP2A03 is indeed running with a clock divider of 12. This can be tested with an oscilloscope on lowest address bit while feeding NOP instructions to the chip, and seeing if the output frequency matches input clock divided by 12.

[sieken]

Although it says RP2A03 (NTSC) on the chip, all tests indicate that it runs on an internal clock divider of 16, just like the RP2A07 (PAL). Tested on lowest address pin while feeding NOP instructions to the CPU yielded a frequency of 312 kHz on the pin. Since NOP is a 2 cycle instruction (including instruction fetch), the divider was calculated as:

divider = 20 MHz / (freq * cycles_per_instruction)

Which was roughly equal to 16.

A more solid test was to measure the output of RP2A03 M2 pin, which is roughly the same as the 6502 phi2 pin. It outputs the the clock frequency post division, with a set duty cycle which varies between the models. Measuring this pin gave us a frequency of 1.25 MHz, and calculations gives us:

divider = 20 MHz / freq = 16.

[sieken]

Added test:

Measuring the lowest address pin while feeding 3-cycle instruction STA (0x85) gave us a frequency of 416 kHz. With the same calculation as above:

divider = 20 MHz / (freq * cycles_per_instruction)

Gives us roughly 16.

[sieken]

After some unsuccessful attempts at communicating with the 2A03, we decided to implement the detect() routine from NESizer, which continuously gives us a divider of 15. So in short: The chips model number (2A03) tells us that it should have a divider of 12, three tests with oscilloscope gives us a divider of 16, and NESizers detect function gives us a divider of 15, which is the one that seems to be working.