Closed rafaelnp closed 4 years ago
For Verilog and SystemVerilog, the only supported tool right now is ModelSim/Questa. Adding support for mixed VHDL/Verilog/SystemVerilog via Vivado xvlog
and for Verilog/SystemVerilog only through verilator
or iverlog
is doable, I'll open issues for those.
Hi,
I am using the hdl_checker in the following environment:
And using this verilog file to test it:
Looking at the log I see the error in the code was not detected, neither in the log file nor in Neovim. Is there something in my configuration/environment missing or wrong?