Terminals of this device

supadupaplex / pfecap

Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET

GNU General Public License v2.0

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Open PengmyHKU opened 3 months ago

PengmyHKU commented 3 months ago

Normally we have two terminals for a capacitor, but why we have an additional terminal called 'qin' in your Verilog-A file? Thank you for your help!

Mr-YangChang commented 3 weeks ago

how can i connect the two components to simulate the model correctly.