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superna9999 / pyamlboot

Amlogic USB Boot Protocol Library
https://pypi.org/project/pyamlboot/
Apache License 2.0
88 stars 33 forks source link

GXL fail to boot on AMD platforms #18

Open superna9999 opened 2 years ago

superna9999 commented 2 years ago

Here's the current log:

$ sudo ./boot.py libretech-cc
Using GX Family boot parameters
ROM: 2.4 Stage: 0.0
Writing /home/narmstrong/projects/amlogic/pyamlboot/files/libretech-cc/u-boot.bin.usb.bl2 at 0xd9000000...
[DONE]
Writing /home/narmstrong/projects/amlogic/pyamlboot/files/usbbl2runpara_ddrinit.bin at 0xd900c000...
[DONE]
Running at 0xd9000000...
[DONE]
Waiting...
[DONE]
ROM: 2.4 Stage: 0.0
Writing /home/narmstrong/projects/amlogic/pyamlboot/files/libretech-cc/u-boot.bin.usb.bl2 at 0xd9000000...
[DONE]
Writing /home/narmstrong/projects/amlogic/pyamlboot/files/usbbl2runpara_runfipimg.bin at 0xd900c000...
[DONE]
Writing /home/narmstrong/projects/amlogic/pyamlboot/files/libretech-cc/u-boot.bin.usb.tpl at 0x200c000...
Traceback (most recent call last):
  File "/home/narmstrong/projects/amlogic/pyamlboot/./boot.py", line 132, in <module>
    usb.load_uboot()
  File "/home/narmstrong/projects/amlogic/pyamlboot/./boot.py", line 89, in load_uboot
    self.write_file(os.path.join(self.bpath, self.TPL_FILE), self.UBOOT_LOAD, large = 64, fill = True)
  File "/home/narmstrong/projects/amlogic/pyamlboot/./boot.py", line 63, in write_file
    self.dev.writeLargeMemory(addr, b, large, fill)
  File "/home/narmstrong/projects/amlogic/pyamlboot/pyamlboot/pyamlboot.py", line 239, in writeLargeMemory
    self._writeLargeMemory(address+offset, data[offset:offset+writeLength], \
  File "/home/narmstrong/projects/amlogic/pyamlboot/pyamlboot/pyamlboot.py", line 220, in _writeLargeMemory
    ep.write(data[offset:offset+blockLength], 1000)
  File "/usr/lib/python3/dist-packages/usb/core.py", line 408, in write
    return self.device.write(self, data, timeout)
  File "/usr/lib/python3/dist-packages/usb/core.py", line 989, in write
    return fn(
  File "/usr/lib/python3/dist-packages/usb/backend/libusb1.py", line 837, in bulk_write
    return self.__write(self.lib.libusb_bulk_transfer,
  File "/usr/lib/python3/dist-packages/usb/backend/libusb1.py", line 938, in __write
    _check(retval)
  File "/usr/lib/python3/dist-packages/usb/backend/libusb1.py", line 602, in _check
    raise USBTimeoutError(_strerror(ret), ret, _libusb_errno[ret])
usb.core.USBTimeoutError: [Errno 110] Operation timed out

The platform is an AMD Ryzen 7 PRO 5850U

superna9999 commented 2 years ago

Intel dumps with pyamlboot + change to write with 4k like the update tool:

pyamlboot-intel-libretech-cc.zip

diff --git a/boot.py b/boot.py
index 5995834..368b321 100755
--- a/boot.py
+++ b/boot.py
@@ -86,7 +86,7 @@ class BootUSB:
         self.init_ddr()
         self.write_file(os.path.join(self.bpath, self.BL2_FILE), self.DDR_LOAD, large = 64)
         self.write_file(os.path.join(self.fpath, self.FIP_FILE), self.BL2_PARAMS, large = 48)
-        self.write_file(os.path.join(self.bpath, self.TPL_FILE), self.UBOOT_LOAD, large = 64, fill = True)
+        self.write_file(os.path.join(self.bpath, self.TPL_FILE), self.UBOOT_LOAD, large = 4096, fill = True)

     def run_uboot(self):
         if ord(self.socid[3]) == 8:

pyamlboot-intel-libretech-cc-4k.zip

aml-update-intel-libretech-cc.zip

superna9999 commented 2 years ago

DDR init fails, instead having:

ROM: 2.2 Stage: 0.8

we have:

ROM: 2.4 Stage: 0.0

which means load of u-boot.bin.usb.bl2 or usbbl2runpara_ddrinit.bin fails to load.