search

supranational / vdf-fpga-round2-results

8 stars 2 forks source link

Estimated Speedup in ASIC #1

Open jon-chuang opened 4 years ago

jon-chuang commented 4 years ago

What is the estimated speedup of the design as an ASIC, given smaller feature sizes and hence higher clock speeds? Could this possibly be 10x?

Further, I notice that the number of clk/sq for pearson_2 is 4. Is there any design where this is faster? Just curious.

Edit: I see the geriatric's is 1 clk. Amazing. I am guessing this is partly due to using fewer LUTs, but this comes at using BRAM, which slows down the clock?

jon-chuang commented 4 years ago

Furthermore, can I ask if the modulus is reconfigurable, or hard coded?